Japanese Patent Application No. 2001-370214 filed on Dec. 4, 2001 is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor memory device, a memory system and an electronic instrument having a plurality of memory block areas.
As shown in FIG. 8, a semiconductor memory device 500 generally has a memory block area 510 and a power source line 520. The power source line 520 is connected to each memory block area 510 and a power voltage is supplied to a memory cell of the memory block area 510.
The present invention may provide a semiconductor memory device, a memory system and an electronic instrument for improving electric characteristics of the semiconductor memory device.
A semiconductor memory device according to the first aspect of the present invention comprises a plurality of memory block areas, a first power source line, and a second power source line electrically separated from the first power source line, the second power source line supplying a potential of which level is equal to the first power source line. The memory block areas include two memory block areas which are simultaneously selected. The first power source line is connected to one of the two memory block areas. The second power source line is connected to the other of the two memory block areas.
In this semiconductor memory device, the two memory block areas simultaneously selected are respectively connected to the first and second power source lines electrically separated from each other. Therefore, noises transmitted onto each of the first and second power source lines are reduced, and a peak current and a steady-state current flowed to each of the first and second power source lines are also reduced. As a result, the electric characteristics of the semiconductor memory device can be improved.
In this semiconductor memory device, the memory block areas may include a plurality of first memory block areas and a plurality of second memory block areas. In this case, the first power source line may be connected to the first memory block areas, and the second power source line may be connected to the second memory block areas. Further, two or more of the first memory block areas may not be simultaneously selected, and two or more of the second memory block areas may not be simultaneously selected. One of the first memory block areas and one of the second memory block areas may be simultaneously selected. By means of this, advantages obtained by the above-described aspect can also be obtained.
In this semiconductor memory device, each of the first and second power source lines may extend along a first direction, and the semiconductor memory device may be divided into first and second areas in the first direction. In this case, the first area may include one of the first memory block areas and one of the second memory block areas, and the second area may include another one of the first memory block areas and another one of the second memory block areas.
In this semiconductor memory device, the two first memory block areas in the first and second areas may be arranged on the side of one of the first and second power source lines, and the two second memory block areas in the first and second areas may be arranged on the side of the other of the first and second power source lines. Otherwise, the first power source line may be provided between the second power source line and the two first memory block areas in the first and second areas, and the second power source line may be provided between the first power source line and the two second memory block areas in the first and second areas.
In this case, the length of a connecting wiring layer for connecting the first power source line with the first memory block area can be minimized. Further, the length of a connecting wiring layer for connecting the second power source line with the second memory block area can be minimized.
In this configuration, the one of the first memory block areas and the another one of the second memory block areas may be simultaneously selected, and the another one of the first memory block areas and the one of the second memory block areas may be simultaneously selected.
As another configuration, the one of the first memory block areas may be provided on the side of one of the first and second power source lines, and the another one of the first memory block areas may be provided on the side of the other of the first and second power source lines. In this case, the one of the second memory block areas may be provided on the side of the other of the first and second power source lines, and the another one of the second memory block areas may be provided on the side of the one of the first and second power source lines. Further, the first and second power source lines may have a crossing portion as viewed form a vertical direction. In this case, the length of a connecting wiring layer for connecting the first power source line with the first memory block area can also be minimized. Further, the length of a connecting wiring layer for connecting the second power source line and the second memory block area can be also set to be shortest.
In this semiconductor memory device, a first terminal group may be arranged along a second direction crossing the first direction at one end in the first direction, and a second terminal group may be arranged along the second direction at the other end in the first direction. The first terminal group may include a terminal for inputting and outputting data of the one of the first memory block areas and the one of the second memory block areas, and the second terminal group may include a terminal for inputting and outputting data of the another one of the first memory block areas and the another one of the second memory block areas.
Further, when the number of bits simultaneously read or written is 2N, the first terminal group may include N-terminals for inputting and outputting data, and the second terminal group may include N-terminals for inputting and outputting data.
In this semiconductor memory device, a data input-output circuit may be provided on one end of the first area in the first direction and on the side of the first terminal group in each of the one of the first memory block areas and the one of the second memory block areas within the first area. This can minimize the distances from the data input-output circuits to the first and second terminal groups.
In this semiconductor memory device, a decoder may be provided at a boundary between the first and second areas. In this case, the first and second terminal groups may further include an address terminal for inputting an address signal. The decoder may be connected to the address terminal and decode the address signal. Therefore, the distances between each address terminal and the decoder can be equalized and the delay of a signal can be reduced.
In this semiconductor memory device, the first and second terminal groups may further include a command terminal for inputting a command signal. In this case, the decoder may be connected to the command terminal and decode the command signal.
As another configuration, the semiconductor memory device may be divided into first and second areas in a first direction, and the one of the first memory block areas may be provided in the first area, and the one of the second memory block areas may be provided in the second area.
The above described memory block areas may be formed of a plurality of sub-blocks. Each of these sub-blocks may be formed by dividing each of the memory block areas in the second direction.
Further, a memory cell forming the memory block areas may be a SRAM.
A memory system according to the second aspect of the present invention comprises the semiconductor memory device according to the first aspect of the present invention described above. Further, an electronic instrument according to the third aspect of the present invention comprises the semiconductor memory device according to the first aspect of the present invention described above.